The invention described herein relates to a Wafer Acceptance Test (WAT) and more specifically to WAT configuration.
Wafer-level electrical testing plays an important role in wafer manufacture, particularly as the cost for post-processes, such as packaging and testing, has increased rapidly. A defective wafer is identified by the testing and disposed of before it undergoes the post-processes. The WAT includes numerous testing items and is crucial for wafer manufacture.
In conventional foundry service, WAT is performed as defined by a preset WAT model, which specifies a constant number of test sites for wafers of specific size. For example, the preset WAT model specifies 5 test sites for an 8-inch wafer, and 9 test sites for a 12-inch wafer. Recently, great advances have been made in wafer manufacturing, and more specific testing has been required to determine product quality. Different WAT models and acceptance criteria are required for different products. Therefore, the standardized WAT configuration cannot satisfy various test requirements of different products. Whenever specific WAT models or acceptance criteria are required, manual intervention is required to confirm the specific test requirement, modify the standard WAT configuration and generate a customized report after the WAT is accomplished as defined by the customized WAT configuration.
Hence, there is a need for a WAT configuration system that addresses the problems arising from the existing technology.